1. Field of the Invention
The present invention relates to a semiconductor device package having a semiconductor device including one or a plurality of semiconductor chips (hereinafter referred to as "chips"), mounted on a substrate, and to a manufacturing method thereof. More specifically, the present invention relates to a semiconductor device package use for flip chip type CSP (Chip Size Package) and manufacturing method thereof.
2. Description of the Background Art
Reduction in size and weight of portable information processing equipments require higher density, smaller size and reduced thickness of a semiconductor device package. A prior art technique proposed to meet the demand includes "a hybrid integrated circuit device" in accordance with Japanese Patent Laying-Open No. 63-84128.
FIG. 15 is a cross sectional view showing the structure of the prior art hybrid integrated circuit device.
Referring to FIG. 15, the hybrid integrated circuit device utilizes COX (Chip on X: X denotes a substrate material selected from an organic film, a printed board, a glass, a silicon wafer and the like) in which an LSI is mounted as a bare chip, on a circuit board. More specifically, a first chip 1 is connected on a thick substrate 21 by a solder connection portion 22, in accordance with the flip chip method.
A second chip 2 is die-bonded to the first chip 1 with rear surfaces of the chips facing to each other, by means of an adhesive 15. The second chip is further connected to thick substrate 21 by wire bonding, through wire 8.
Further, the first and second chips are coated to be covered entirely by a chip coat resin 20.
Another SMD (Surface Mount Device) 40 is mounted by means of a lead 41 as shown in the figure, on thick substrate 21.
However, in the conventional mounting structure shown in FIG. 15, the chip is directly mounted on thick substrate 21 and not packaged. Therefore, it is not possible to implement the mounting structure shown in FIG. 15 on the thick substrate simply by the step of conventional SMD (Surface Mount Technology) in which reflow soldering is performed collectively after components are mounted.
More specifically, in order to implement the mounting structure shown in FIG. 15, it is necessary to newly add, to an existing assembly line of each plant, a dedicated production line including a flip-chip-mounting apparatus, a die bonding apparatus, a wire bonding apparatus and a chip coating apparatus. This requires considerable capital investment.
In the mounting structure shown in FIG. 15, the chip is not packaged. Therefore, if it is found after mounting that the mounted chip is defective, it has been difficult to replace only the defective chip.
Further, in the prior art example shown in FIG. 15, the first chip is connected to the circuit board in accordance with the flip chip method and, thereafter, the second chip is connected to the circuit board by wire bonding. This possibly causes a problem that the solder connecting portion 22 of the flip-chip-connected first chip 1 is damaged by load or ultrasonic output at the time of wire bonding of the second chip, resulting in failure of electrical connection. Further, as the entire mounted structure is chip coated, chip coat resin 20 extends considerably wide, causing a problem that a length 24 from a chip edge to an outer periphery of a mold is made too long.
Conventionally, it has been a common practice to introduce a resin into a gap between a chip and the substrate in a structure where only one chip not having a stacked structure is flip-chip-mounted, in order to relax thermal stress derived from difference in coefficient of thermal expansion. The amount of resin introduced, however, has not been studied at all.
As the LSI comes to have higher density, larger number of pins and, eventually, finer pitch, the gap between the chip and the substrate naturally becomes narrower. For a stacked type CSP (Chip Size Package), one having the gap between the chip and the interconnection of 25 to 30 .mu.m and the gap between the chip and the substrate of about 50 .mu.m has been under development. In order to fill a sealing resin into such a narrow gap, viscosity of the resin should naturally be made lower.
If the viscosity of resin is low, however, there possibly arises a problem that a large fillet (flow out of the resin) is formed at a chip edge, as will be described later.